Subject Name:
Fundamentals of Logic Design
Subject Code:
CCE1102
Faculty:
Faculty of Engineering
Bylaw:
7500
Department:
Electrical Engineering
Elective/Compulsory:
Compulsory
Course Status:
Failure And In Total Subject
Course Type:
Faculty requirment
Course Contents:
Logicgate networks Karnaugh maps QuineMcCluskey method Combinational networks Multiplexers Demultiplexers Decoders Encoders Programmable logic Sequential networks Flipflops Counters Registers State graphs Mooretype networks Mealytype networks
Teaching Hours:
5
Credit Hours:
0
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